1. Field of the Invention
This invention relates to the structure of a field effect transistor (FET), an integrated circuit (IC) formed by integrating FETs on a single substrate, or other such semiconductor device, and to a method of fabricating a semiconductor device of such structure.
2. Description of the Related Art
Recent years have seen the use of semiconductor devices employing silicon-on-insulator (SOI) structure as high-voltage devices and high-speed devices. Particularly in the area of thin-film SOI, research is being conducted toward optimizing reduction of power consumption and enhancement of current driving characteristics.
The formation of the diffusion layer of the thin-film (SOI) structure will be explained first with reference to the sectional view in FIG. 33.
A gate oxide film 2 is formed on a SIMOX (separation-by-implantation-of-oxygen) substrate 20 having an buried oxide layer 19 sandwiched between a single crystalline silicon substrate 1 and an active region 18.
The SIMOX substrate 20 is formed by using an ion implantation method to implant oxygen ions into the single crystalline silicon substrate 1 from the surface thereof, forming the buried oxide layer 19 (a silicon oxide layer) in the interior of the single crystalline silicon substrate 1 by an ensuing annealing, and forming the active region 18 near the surface.
The implanted oxide layer 19 has a thickness of about 80 nm and the active region 18 a thickness of about 150 nm.
The gate oxide film 2 is formed, a gate 4 (a polysilicon film) is formed thereon, an mask oxide film 5 is formed on the surface of the gate 4, and impurity ions are implanted into the entire surface by an ion implantation method.
An interlayer insulator film (not shown) is formed on the SIMOX substrate 20. The result is annealed in an inert gas to diffuse the implanted impurity ions into diffusion layer regions 15, 15 (the active region 18) on opposite sides of the gate 4, simultaneously activating the impurity ions to form a source and a drain.
Since ion implantation injects energized impurity ions through the crystal of the host material, it generally causes dislocations in the crystal structure.
In the ordinary structure for forming a device in the single crystalline silicon substrate 1, the thickness of the single crystalline silicon substrate 1 corresponds to the thickness of the active region 18 of the SOI structure. Because of this, not all of the crystals in the thickness direction are dislocated and damaged by the ion implantation.
The annealing for impurity diffusion and activation after interlayer insulator film formation therefore enables the crystals dislocated during ion implantation to recover easily using the undislocated crystals as seeds.
In the SOI structure, on the other hand, all of the active region 18 of the buried oxide layer 19 formed by ion implantation is amorphous. The crystal grains therefore enlarge but do not become single crystal owing to the annealing after formation of the interlayer insulator film.
In other words, when a device is formed on the single crystalline silicon substrate 1, seed crystals enabling crystal recovery are present after ion implantation but are not present in the case of the thin-film SOI structure because the active region 18 is amorphized throughout.
Thus when the diffusion layer region 15 is formed in the thin-film SOI structure by the conventional method, the active region 18 is thin, so that it exhibits high sheet resistance, and is amorphized by the ion implantation. This results in a great increase in the contact resistance of the source and drain formed in the diffusion layer regions 15, 15 of the active region 18.
This phenomenon arises both in the case of implanting P-type impurity ions and in the case of implanting N-type impurity ions.
In a thin-film (SOI) structure semiconductor device, therefore, contact resistance is reduced by forming a refractory metal material or a silicide thereof in the diffusion layer region. Since this involves use of a different type of material, however, the compatibility of the process is poor.
The formation of the diffusion layer of a P-type conductivity field effect transistor (FET) formed on a single crystalline silicon substrate will now be explained.
In the prior art, the P-type diffusion layer region to constitute the diffusion layer region of the P-type conductivity FET is obtained by ion implantation of boron (.sup.11 B.sup.+)
As FET geometry is scaled down to the sub-micron range, however, the diffusion layer for constituting the source and drain has to be made increasingly shallow. The formation of the required shallow diffusion layer by boron ion implantation has become difficult.
This is because boron, being a light element, has a large implantation range, and this, plus the effect of channeling, makes it hard to obtain a shallow diffusion layer.
Channeling refers to the deep penetration of ions into the crystal without significant scattering when the direction of ion incidence coincides with the direction of the voids enclosed by rows of atoms on the side of the single crystalline silicon substrate to be implanted.
Another problem of boron is that its large diffusion coefficient during annealing promotes the occurrence of secondary diffusion and hinders the formation of a shallow diffusion layer.
Although a shallow diffusion layer can be formed by reducing the boron implantation energy, lowering the acceleration energy enlarges the channeling critical angle and makes it impossible to suppress channeling at the conventional implantation angle of around 6-7 degrees.
Another method proposed for reducing implantation depth is to implant boron fluoride (.sup.49 BF.sub.2.sup.+), which has a large mass number, in place of boron.
It is known that a larger beam current can be secured with boron fluoride (.sup.49 BF.sub.2.sup.+) than with boron (.sup.11 B.sup.+) and that, therefore, the implantation depth is about one fourth that of boron (.sup.11 B.sup.+) for the same acceleration energy. In effect, this enables low acceleration energy implantation.
When boron fluoride (.sup.49 BF.sub.2.sup.+) is used and the annealing temperature is 900.degree. C. or lower, however, the ion-implanted fluorine remains in the silicon substrate. Since these fluorine ions remain at lattice defects and dislocation in the single crystalline silicon substrate, they obstruct recovery of the silicon crystallinity and affect the transistor characteristics since they are a cause of leak current occurring at the pn junctions and the like.
In addition, channeling occurring during ion implantation of boron fluoride (.sup.49 BF.sub.2.sup.+) hinders formation of a shallow P-type diffusion layer.
An example of a prior-art technique currently used to suppress channeling in boron implantation will be explained with reference to the sectional view of FIG. 34.
As shown in FIG. 34, there can be used a single crystalline silicon substrate 1 of N-type conductivity or, instead, a single crystalline silicon substrate obtained by implanting N-type impurity ions in a single crystalline silicon substrate 1 and annealing it to form a diffused N-type conductivity region called an N-well.
A gate oxide film 2 and a gate 4 are formed on the single crystalline silicon substrate 1. Next, the surface of the diffusion layer region 15 is implanted with silicon ions using the photoresist 16 used for forming the gate 4 as an ion implantation mask.
This silicon ion implantation forms an amorphous film 14 with an irregular crystal lattice on the surface of the diffusion layer region 15 of the single crystalline silicon substrate 1. The photoresist 16 is then removed and P-type conductivity impurity ions are implanted in the diffusion layer region 15 by self-alignment relative to the gate 4.
The amorphous film 14 having the irregularly positioned crystal lattice suppresses occurrence of channeling and the impurity ions are implanted in a shallow depth region of the diffusion layer region 15 of the single crystalline silicon substrate 1.
Next, impurity activation and recrystallization of the amorphous layer 14 are effected by annealing in an inert gas to obtain a shallow diffusion layer constituting a source 11 and drain 12 compatible with FET geometry scaled down to the sub-micron range.
In the semiconductor device explained with reference to FIG. 34, the diffusion layer region 15 constituting the source and drain is obtained as a shallow diffusion layer. Since the silicon ions of certain energy damage the surface of the single crystalline silicon substrate 1 at the diffusion layer region 15, however, secondary defects and the like occur in the vicinity of the interface between the amorphous film 14 and the single crystalline silicon substrate 1 even after annealing. These defects prevent complete recovery of crystallinity.
Owing to this failure to secure perfect crystallinity, the breakdown voltage of the pn junctions formed between the single crystalline silicon substrate 1, or the N-type conductivity region called an N-well formed in the single crystalline silicon substrate 1, and the diffusion layer region 15 is degraded to increases the leak current across the junctions. This is discussed, for example, by C.Carter et al. in Appl. Phys. Lett., Vol 44, No. 4, 15 Feb. 1984, PP.459-461.
As explained in the foregoing, the prior-art fabrication method cannot easily form the diffusion layer of a field effect transistor according to the thin-film SOI structure so as to be free of crystal defects and low in resistance. It is also incapable of easily forming the shallow P-type conductivity diffusion layer for constituting the source and drain of a small-geometry FET formed on a single crystalline silicon substrate so as to be free of crystal defects and exhibit good reproducibility.